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256k x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. w03.pm5 C rev.3/97 ? 1997, micron technology, inc. 256k x 16 fpm dram 1 technology, inc. pin assignment (top view) dram MT4C16257 features ? industry-standard x16 pinouts, timing, functions and packages ? high-performance cmos silicon-gate process ? single +5v 10% power supply ? all inputs, outputs and clocks are ttl-compatible ? 512-cycle refresh in 8ms (9 rows, 9 column addresses) ? refresh modes: ras#-only, cas#-before-ras# (cbr), optional extended and hidden ? fast page mode access cycle ? byte write access cycle ? byte read access cycle options marking ? timing 60ns access -6 ? package plastic soj (400 mil) dj ? part number example: MT4C16257dj-6 general description the MT4C16257 is a randomly accessed, solid-state memory containing 4,194,304 bits organized in a x16 con- figuration. the MT4C16257 has both byte write and word write access cycles via two cas# pins. the MT4C16257 cas# function and timing are deter- mined by the first cas# (casl# or cash#) to transition low and by the last to transition back high. use of only one of the two results in a byte write cycle. casl# transitioning low selects a write cycle for the lower byte (dq1-dq8) and cash# transitioning low selects a write cycle for the upper byte (dq9-dq16). byte read cycles are achieved through casl# or cash# in the same man- ner during read cycles for the MT4C16257. functional description each bit is uniquely addressed through the 18 address bits during read or write cycles. these are entered 9 bits (a0 -a8) at a time. ras# is used to latch the first 9 bits and cas# the latter 9 bits. key timing parameters speed t rc t rac t pc t aa t cac t rp -6 110ns 60ns 35ns 30ns 15ns 40ns the cas# control also determines whether the cycle will be a refresh cycle (ras#-only) or an active cycle (read, write or read write) once ras# goes low. the casl# and cash# inputs internally generate a cas# signal functioning in an identical manner to the single cas# input on the other 256k x 16 drams. the key difference is each cas# controls its corresponding dq tristate logic (in conjunction with oe# and we#). casl# controls dq1 through dq8 and cash# controls dq9 through dq16. the MT4C16257 cas# function is determined by the first cas# (casl# or cash# ) to transition low and the last one to transition back high. the two cas# controls give the MT4C16257 both byte read and byte write cycle capabilities. a logic high on we# dictates read mode while a logic low on we# dictates write mode. during a write cycle, data-in (d) is latched by the falling edge of we# or cas#, whichever occurs last. taking we# low will ini- note: the # symbol indicates signal is active low. 40-pin soj (da-6) vcc dq1 dq2 dq3 dq4 vcc dq5 dq6 dq7 dq8 nc nc we# ras# nc a0 a1 a2 a3 vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 vss dq16 dq15 dq14 dq13 vss dq12 dq11 dq10 dq9 nc casl# cash# oe# a8 a7 a6 a5 a4 vss
256k x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. w03.pm5 C rev.3/97 ? 1997, micron technology, inc. 256k x 16 fpm dram 2 technology, inc. functional block diagram 9 casl# cas# ras# 9 9 no. 2 clock generator refresh controller no. 1 clock generator 512 x 512 x 16 memory array vcc vss 9 oe# dq1 dq16 refresh counter cash# a0 a1 a2 a3 a4 a5 a6 a7 a8 lower byte (dq1-dq8) upper byte (dq9-dq16) 8 512 512 x 16 16 9 512 we# 8 16 data-out buffer sense amplifiers i/o gating row decoder row address buffers (9) column address buffer column decoder data-in buffer early write detection circuit
256k x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. w03.pm5 C rev.3/97 ? 1997, micron technology, inc. 256k x 16 fpm dram 3 technology, inc. and strobing-in different column addresses, thus executing faster memory cycles. returning ras# high terminates the fast page mode operation. returning ras# and cas# high terminates a memory cycle and decreases chip current to a reduced standby level. the chip is also preconditioned for the next cycle during the ras# high time. memory cell data is retained in its correct state by maintaining power and executing any ras# cycle (read, write) or ras# refresh cycle (ras#-only, cbr, or hidden) so that all 512 combinations of ras# ad- dresses (a0 -a8) are executed at least every 8ms, regardless of sequence. the cbr refresh cycle will also invoke the refresh counter and controller for row-address control. extended refresh is a cbr refresh performed at the extended refresh rate with cmos input levels. this mode provides a lower-current data-retention cycle. figure 1 word and byte write example stored data 1 1 0 1 1 1 1 1 ras# casl# we# x = not effective (don't care) address 1 address 0 0 1 0 1 0 0 0 0 word write lower byte write cash# input data 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 x x x x x x x x input data 1 1 0 1 1 1 1 1 input data stored data 1 1 0 1 1 1 1 1 input data stored data 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 stored data 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 x x x x x x x x 1 0 1 0 1 1 1 1 upper byte (dq9-dq16) of word lower byte (dq1-dq8) of word tiate a write cycle, selecting dq1 through dq16. if we# goes low prior to cas# going low, the output pin(s) remain open (high-z) until the next cas# cycle. if we# goes low after cas# goes low and data reaches the output pins, data-out (q) is activated and retains the se- lected cell data as long as cas# and oe# remain low (regardless of we# or ras#). this late we# pulse results in a read write cycle. the 16 data inputs and 16 data outputs are routed through 16 pins using common i/o, and pin direction is controlled by oe#. fast page mode operations allow faster data opera- tions (read, write or read-modify-write) within a row-address-defined (a0 -a8) page boundary. the fast page mode cycle is always initiated with a row address strobed-in by ras# followed by a column address strobed- in by cas#. cas# may be toggled by holding ras# low functional description (continued)
256k x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. w03.pm5 C rev.3/97 ? 1997, micron technology, inc. 256k x 16 fpm dram 4 technology, inc. byte access cycle the byte write mode is determined by the use of casl# and cash#. enabling casl# will select a lower byte write cycle (dq1-dq8) while enabling cash# will select an upper byte write cycle (dq9-dq16). enabling both casl# and cash# selects a word write cycle. the MT4C16257 can be viewed as two 256k x 8 drams which have common input controls, with the exception of the cas# inputs. figure 1 illustrates the MT4C16257 byte write and word write cycles. the MT4C16257 also has byte read and word read cycles. figure 2 illustrates the MT4C16257 byte read and word read cycles. additionally, both bytes must always be of the same mode of operation if both bytes are active. a cas# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. for example, an early write on one byte and a late write on the other byte is not allowed during the same cycle. however, an early write on one byte and, after a cas# precharge has been satisfied, a late write on the other byte is permissible. stored data 1 1 0 1 1 1 1 1 ras# casl# we# z = high-z address 1 address 0 0 1 0 1 0 0 0 0 word read lower byte read stored data 1 1 0 1 1 1 1 1 cash# output data 1 1 0 1 1 1 1 1 stored data 1 1 0 1 1 1 1 1 z z z z z z z z output data 1 1 0 1 1 1 1 1 output data 1 1 0 1 1 1 1 1 output data 1 1 0 1 1 1 1 1 stored data 1 1 0 1 1 1 1 1 upper byte (dq9-dq16) of word lower byte (dq1-dq8) of word 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 z z z z z z z z z z z z z z z z 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 figure 2 word and byte read example
256k x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. w03.pm5 C rev.3/97 ? 1997, micron technology, inc. 256k x 16 fpm dram 5 technology, inc. truth table addresses function ras# casl# cash# we# oe# t r t c dqs notes standby h h ? xh ? x x x x x high-z read: word l l l h l row col data-out read: lower byte l l h h l row col lower byte, data-out upper byte, high-z read: upper byte l h l h l row col lower byte, high-z upper byte, data-out write: word l l l l x row col data-in (early write) write: lower l l h l x row col lower byte, data-in byte (early) upper byte, high-z write: upper l h l l x row col lower byte, high-z byte (early) upper byte, data-in read write l l l h ? ll ? h row col data-out, data-in 1, 2 page-mode 1st cycle l h ? lh ? l h l row col data-out 2 read 2nd cycle l h ? lh ? l h l n/a col data-out 2 page-mode 1st cycle l h ? lh ? l l x row col data-in 1 write 2nd cycle l h ? lh ? l l x n/a col data-in 1 page-mode 1st cycle l h ? lh ? lh ? ll ? h row col data-out, data-in 1, 2 read-write 2nd cycle l h ? lh ? lh ? ll ? h n/a col data-out, data-in 1, 2 hidden read l ? h ? l l l h l row col data-out 2 refresh write l ? h ? l l l l x row col data-in 1, 3 ras#-only l h h x x row n/a high-z refresh cbr refresh h ? l l l x x x x high-z 4 note: 1. these write cycles may also be byte write cycles (either casl# or cash# active). 2. these read cycles may also be byte read cycles (either casl# or cash# active). 3. early write only. 4. at least one of the two cas# signals must be active (casl# or cash#).
256k x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. w03.pm5 C rev.3/97 ? 1997, micron technology, inc. 256k x 16 fpm dram 6 technology, inc. absolute maximum ratings* voltage on any pin relative to v ss .................... -1v to +7v operating temperature, t a (ambient) .......... 0 c to +70 c storage temperature (plastic) .................... -55 c to +150 c power dissipation .......................................................... 1.2w short circuit output current ..................................... 50ma no-connect pins not to exceed ........................................ v cc *stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions (notes: 1, 5, 6) (v cc = +5v 10%) parameter/condition symbol min max units notes supply voltage v cc 4.5 5.5 v input high (logic 1) voltage, all inputs v ih 2.4 v cc +1 v input low (logic 0) voltage, all inputs v il -1.0 0.8 v input leakage current any input 0v v in v cc +1.0v i i -2 2 m a (all other pins not under test = 0v) output leakage current (dq is disabled; 0v v out 5.5v) i oz -10 10 m a output levels v oh 2.4 v output high voltage (i out = -5ma) output low voltage (i out = 4.2ma) v ol 0.4 v parameter/condition symbol -6 units notes standby current: (ttl) i cc 1 2ma (ras# = cas# = v ih ) standby current: (cmos) i cc 2 1ma22 (ras# = cas# = v cc -0.2v) operating current: random read/write average power supply current i cc 3 195 ma 3, 34 (ras#, cas#, address cycling: t rc = t rc [min]) operating current: fast page mode average power supply current i cc 4 120 ma 3, 34 (ras# = v il , cas#, address cycling: t pc = t pc [min]; t cp, t asc = 10ns) refresh current: ras# only average power supply current i cc 5 195 ma 3, 34 (ras# cycling, cas# = v ih : t rc = t rc [min]) refresh current: cbr average power supply current i cc 6 180 ma 3, 4 (ras#, cas#, address cycling: t rc = t rc [min]) max
256k x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. w03.pm5 C rev.3/97 ? 1997, micron technology, inc. 256k x 16 fpm dram 7 technology, inc. ac electrical characteristics (notes: 5, 6, 7, 8, 9, 10, 11, 12) (v cc = +5v 10%) ac characteristics -6 parameter sym min max units notes access time from column address t aa 30 ns column-address hold time (referenced to ras#) t ar 50 ns column-address setup time t asc 0 ns 26 row-address setup time t asr 0 ns column-address to we# delay time t awd 55 ns 18 access time from cas# t cac 15 ns 28 column-address hold time t cah 10 ns 26 cas# pulse width t cas 15 10,000 ns 31 cas# hold time (cbr refresh) t chr 10 ns 4, 27 last cas# going low to first cas# returning high t clch 10 ns 29 cas# to output in low-z t clz 3 ns 28 cas# precharge time t cp 10 ns 13 access time from cas# precharge t cpa 35 ns 28 cas# to ras# precharge time t crp 10 ns 27 cas# hold time t csh 60 ns 27 cas# setup time (cbr refresh) t csr 10 ns 4, 26 cas# to we# delay time t cwd 40 ns 18, 26 write command to cas# lead time t cwl 15 ns 23, 27 data-in hold time t dh 10 ns 19, 28 data-in setup time t ds 0 ns 19, 28 output disable time t od 3 15 ns 25, 33 output enable time t oe 15 ns 28 oe# hold time from we# during read-modify-write cycle t oeh 15 ns 26 output buffer turn-off delay t off 3 15 ns 17, 25, 28 oe# setup prior to ras# during hidden refresh cycle t ord 0 ns fast-page-mode read or write cycle time t pc 35 ns 30 fast-page-mode read-write cycle time t prwc 85 ns 30 access time from ras# t rac 60 ns ras# to column-address delay time t rad 15 ns 15 row-address hold time t rah 10 ns ras# pulse width t ras 60 10,000 ns ras# pulse width (page mode) t rasp 60 100,000 ns random read or write cycle time t rc 110 ns ras# to cas# delay time t rcd 20 ns 14, 26 read command hold time (referenced to cas#) t rch 0 ns 16, 23, 27 capacitance parameter symbol max units notes input capacitance: a0-a8 c i 1 5pf2 input capacitance: ras#, casl#, cash#, we#, oe# c i 2 7pf2 input/output capacitance: dq c io 7pf2
256k x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. w03.pm5 C rev.3/97 ? 1997, micron technology, inc. 256k x 16 fpm dram 8 technology, inc. ac electrical characteristics (notes: 5, 6, 7, 8, 9, 10, 11, 12) (vcc = +5v 10%) ac characteristics -6 parameter sym min max units notes read command setup time t rcs 0 ns 23, 26 refresh period (512 cycles) t ref 8 ms ras# precharge time t rp 40 ns ras# to cas# precharge time t rpc 10 ns read command hold time (referenced to ras#) t rrh 0 ns 16 ras# hold time t rsh 15 ns 32 read write cycle time t rwc 150 ns ras# to we# delay time t rwd 85 ns 18 write command to ras# lead time t rwl 15 ns 23 transition time (rise or fall) t t250ns write command hold time t wch 10 ns 23, 32 write command hold time (referenced to ras#) t wcr 45 ns 23 write command setup time t wcs 0 ns 18, 23, 26 write command pulse width t wp 10 ns 23 we# hold time (cbr refresh) t wrh 10 ns we# setup time (cbr refresh) t wrp 10 ns
256k x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. w03.pm5 C rev.3/97 ? 1997, micron technology, inc. 256k x 16 fpm dram 9 technology, inc. notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v cc = 4.5v; f = 1 mhz. 3. i cc is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the output open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0 c t a 70 c) is ensured. 6. an initial pause of 100 m s is required after power-up, followed by eight ras# refresh cycles (ras#-only or cbr), before proper device operation is ensured. the eight ras# cycle wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 5ns. 8. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il (or between v il and v ih ). 9. in addition to meeting the transition rate specifica- tion, all input signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 10. if cas# = v ih , data output is high-z. 11. if cas# = v il , data output may contain data from the last valid read cycle. 12. measured with a load equivalent to two ttl gates and 100pf, v ol = 0.80 and v oh = 2v. 13. if cas# is low at the falling edge of ras#, q will be maintained from the previous cycle. to initiate a new cycle and clear the q buffer, cas# must be pulsed high for t cp. 14. the t rcd (max) limit is no longer specified. t rcd (max) was specified as a reference point only. if t rcd was greater than the specified t rcd (max) limit, then access time was controlled exclusively by t cac ( t rac [min] no longer applied). with or without the t rcd limit, t aa and t cac must always be met. 15. the t rad (max) limit is no longer specified. t rad (max) was specified as a reference point only. if t rad was greater than the specified t rad (max) limit, then access time was controlled exclusively by t aa ( t rac and t cac no longer applied). with or without the t rad (max) limit, t aa, t rac and t cac must always be met. 16. either t rch or t rrh must be satisfied for a read cycle. 17. t off (max) defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the 3ns minimum is a parameter guaranteed by design. 18. t wcs, t rwd, t awd and t cwd are restrictive operating parameters in late write and read- modify-write cycles only. if t wcs 3 t wcs (min), the cycle is an early write cycle and the data output will remain an open circuit throughout the entire cycle. if t rwd 3 t rwd (min), t awd 3 t awd (min) and t cwd 3 t cwd (min), the cycle is a read write and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of q (at access time and until cas# or oe# goes back to v ih ) is indeterminate. oe# held high and we# taken low after cas# goes low result in a late write (oe#-controlled) cycle. 19. these parameters are referenced to cas# leading edge in early write cycles and we# leading edge in late write or read-modify-write cycles. 20. during a read cycle, if oe# is low then taken high before cas# goes high, q goes open. if oe# is tied permanently low, a late write or read- modify-write operation is not possible. 21. a hidden refresh may also be performed after a write cycle. in this case, we# = low and oe# = high. 22. all other inputs at v cc -0.2v. 23. write command is defined as we# going low. 24. late write and read-modify-write cycles must have both t od and t oeh met (oe# high during write cycle) in order to ensure that the output buffers will be open during the write cycle. the dqs will provide the previously written data if cas# remains low and oe# is taken back low after t oeh is met. if cas# goes high prior to oe# going back low, the dqs will remain open. 25. the dqs open during read cycles once t od or t off occur. if cas# goes high before oe#, the dqs will open regardless of the state of the oe#. if cas# stays low while oe# is brought high, the dqs will open. if oe# is brought back low (cas# still low), the dqs will provide the previously read data. 26. the first casx# edge to transition low. 27. the last casx# edge to transition high. 28. output parameter (dqx) is referenced to correspond- ing cas# input, dq1-dq8 by casl# and dq9-dq16 by cash#. 29. last falling casx# edge to first rising casx# edge. 30. last rising casx# edge to next cycles last rising casx# edge. 31. each casx# must meet minimum pulse width. 32. last casx# to go low. 33. all dqs controlled, regardless casl# and cash#. 34. column address changed once each cycle.
256k x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. w03.pm5 C rev.3/97 ? 1997, micron technology, inc. 256k x 16 fpm dram 10 technology, inc. timing parameters -6 symbol min max units t aa 30 ns t ar 50 ns t asc 0 ns t asr 0 ns t cac 15 ns t cah 10 ns t cas 15 10,000 ns t clch 10 ns t clz 3 ns t crp 10 ns t csh 60 ns t od 3 15 ns t oe 15 ns read cycle t rrh t clz t cac t rac t aa valid data open t off t rch row t rcs t asc t rah t rad t ar t cah t rcd t cas t rsh t csh t rp t rc t ras t crp t asr row open ras# v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il t od t oe t oes oe# v v ih il column t clch cash#/casl# we# note 1 don?t care undefined -6 symbol min max units t off 3 15 ns t rac 60 ns t rad 15 ns t rah 10 ns t ras 60 10,000 ns t rc 110 ns t rcd 20 ns t rch 0 ns t rcs 0 ns t rp 40 ns t rrh 0 ns t rsh 15 ns
256k x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. w03.pm5 C rev.3/97 ? 1997, micron technology, inc. 256k x 16 fpm dram 11 technology, inc. don? care undefined v v ih il valid data row column row t ds t wp t wch t wcs t wcr t rwl t cwl t cah t asc t rah t asr t rad t ar t cas t rsh t csh t rcd t crp t ras t rc t rp v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t dh t clch we# casl#/cash# early write cycle timing parameters -6 symbol min max units t ar 50 ns t asc 0 ns t asr 0 ns t cah 10 ns t cas 15 10,000 ns t clch 10 ns t crp 10 ns t csh 60 ns t cwl 15 ns t dh 10 ns t ds 0 ns t rad 15 ns -6 symbol min max units t rah 10 ns t ras 60 10,000 ns t rc 110 ns t rcd 20 ns t rp 40 ns t rsh 15 ns t rwl 15 ns t wch 10 ns t wcr 45 ns t wcs 0 ns t wp 10 ns
256k x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. w03.pm5 C rev.3/97 ? 1997, micron technology, inc. 256k x 16 fpm dram 12 technology, inc. read write cycle (late write and read-modify-write cycles) valid d out valid d in row column row v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# open open t oe t od t cac t rac t aa t clz t ds t dh t awd t wp t rwl t cwl t cwd t rwd t rcs t asc t cah t ar t asr t rad t crp t rcd t cas t rsh t csh t ras t rwc t rp t rah oe# t oeh t clch we# casl#/cash# don?t care undefined -6 symbol min max units t od 3 15 ns t oe 15 ns t oeh 15 ns t rac 60 ns t rad 15 ns t rah 10 ns t ras 60 10,000 ns t rcd 20 ns t rcs 0 ns t rp 40 ns t rsh 15 ns t rwc 150 ns t rwd 85 ns t rwl 15 ns t wp 10 ns timing parameters -6 symbol min max units t aa 30 ns t ar 50 ns t asc 0 ns t asr 0 ns t awd 55 ns t cac 15 ns t cah 10 ns t cas 15 10,000 ns t clch 10 ns t clz 3 ns t crp 10 ns t csh 60 ns t cwd 40 ns t cwl 15 ns t dh 10 ns t ds 0 ns
256k x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. w03.pm5 C rev.3/97 ? 1997, micron technology, inc. 256k x 16 fpm dram 13 technology, inc. t oe 15 ns t off 3 15 ns t pc 35 ns t rac 60 ns t rad 15 ns t rah 10 ns t rasp 60 100,000 ns t rcd 20 ns t rch 0 ns t rcs 0 ns t rp 40 ns t rrh 0 ns t rsh 15 ns timing parameters -6 symbol min max units t aa 30 ns t ar 50 ns t asc 0 ns t asr 0 ns t cac 15 ns t cah 10 ns t cas 15 10,000 ns t clch 10 ns t clz 3 ns t cp 10 ns t cpa 35 ns t crp 10 ns t csh 60 ns t od 3 15 ns fast-page-mode read cycle valid data valid data valid data column column column row row don?t care undefined t rcs t cah t asc t cp t rsh t cp t cp t cas, t rcd t crp t pc t csh t rasp t rp t cah t asc t cah t asc t ar t rah t rad t asr t rcs t rch t rch t rcs t rrh t rch t off t cac t cpa t aa t clz t off t cac t cpa t aa t clz t off t cac t rac t aa t clz t oe t od t oe t od t oe t od open open v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t clch t cas, t clch t cas, t clch we# casl#/cash# -6 symbol min max units
256k x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. w03.pm5 C rev.3/97 ? 1997, micron technology, inc. 256k x 16 fpm dram 14 technology, inc. fast-page-mode early-write cycle t ds t dh t ds t dh t ds t dh t wcr valid data valid data valid data t rwl t wp t cwl t wch t wcs t wp t cwl t wch t wcs t wp t cwl t wch t wcs t cah t asc t cah t asc t cah t asc t rah t asr t rad t ar column column column row row t cp t rsh t cp t cp t rcd t crp t pc t csh t rasp t rp v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t cas, t clch t cas, t clch t cas, t clch we# casl#/cash# don?t care undefined -6 symbol min max units t pc 35 ns t rad 15 ns t rah 10 ns t rasp 60 100,000 ns t rcd 20 ns t rp 40 ns t rsh 15 ns t rwl 15 ns t wch 10 ns t wcr 45 ns t wcs 0 ns t wp 10 ns timing parameters -6 symbol min max units t ar 50 ns t asc 0 ns t asr 0 ns t cah 10 ns t cas 15 10,000 ns t clch 10 ns t cp 10 ns t crp 10 ns t csh 60 ns t cwl 15 ns t dh 10 ns t ds 0 ns
256k x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. w03.pm5 C rev.3/97 ? 1997, micron technology, inc. 256k x 16 fpm dram 15 technology, inc. fast-page-mode read-write cycle (late write and read-modify-write cycles) don? care undefined t od t oe t od t oe t od t oe open d out valid d in valid d out valid d in valid d out valid d in valid open t dh t ds t aa t cpa t clz t cac t dh t ds t aa t cpa t clz t cac t dh t ds t aa t clz t cac t rac t wp t cwl t rwl t cwd t awd t wp t cwl t cwd t awd t wp t cwl t cwd t awd t rcs t rwd t asr t rah t asc t rad t ar t cah t asc t cah t asc t cah t cp t rsh t cp t rp t rasp t cp t rcd t csh t pc note 1 t crp row column column column row v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t prwc oeh t cas, t clch t cas, t clch t cas, t clch we# casl#/cash# note: t pc is for late write only. -6 symbol min max units t ds 0 ns t od 3 15 ns t oe 15 ns t oeh 15 ns t pc 35 ns t prwc 85 ns t rac 60 ns t rad 15 ns t rah 10 ns t rasp 60 100,000 ns t rcd 20 ns t rcs 0 ns t rp 40 ns t rsh 15 ns t rwd 85 ns t rwl 15 ns t wp 10 ns timing parameters -6 symbol min max units t aa 30 ns t ar 50 ns t asc 0 ns t asr 0 ns t awd 55 ns t cac 15 ns t cah 10 ns t cas 15 10,000 ns t clch 10 ns t clz 3 ns t cp 10 ns t cpa 35 ns t crp 10 ns t csh 60 ns t cwd 40 ns t cwl 15 ns t dh 10 ns
256k x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. w03.pm5 C rev.3/97 ? 1997, micron technology, inc. 256k x 16 fpm dram 16 technology, inc. ras#-only refresh cycle (addresses; oe#, we# = dont care) cbr refresh cycle (addresses and oe# = dont care) note: 1. t wrp and t wrh are for system design reference only. the we# signal is actually a dont care at ras# time during a cbr refresh. however, we# should be held high at ras# time during a cbr refresh to ensure compatibility with other drams which require we# high at ra s# time during a cbr refresh. row v v ih il v v ih il addr v v ih il ras# t rc t ras t rp t crp t asr t rah row open q v v oh ol t rpc casl#/cash# t rp v v ih il ras# t ras open t chr t csr v v ih il v v oh ol dq t rp t ras t rpc t csr t rpc t chr t cp v v ih il t wrp t wrh t wrp t wrh we# don?t care undefined note 1 casl#/cash# -6 symbol min max units t ras 60 10,000 ns t rc 110 ns t rp 40 ns t rpc 10 ns t wrh 10 ns t wrp 10 ns timing parameters -6 symbol min max units t asr 0 ns t chr 10 ns t cp 10 ns t crp 10 ns t csr 10 ns t rah 10 ns
256k x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. w03.pm5 C rev.3/97 ? 1997, micron technology, inc. 256k x 16 fpm dram 17 technology, inc. timing parameters -6 symbol min max units t aa 30 ns t ar 50 ns t asc 0 ns t asr 0 ns t cac 15 ns t cah 10 ns t chr 10 ns t clz 3 ns t crp 10 ns t od 3 15 ns hidden refresh cycle 21 (we# = high; oe# = low) don? care undefined t clz t off open valid data open column row t cac t rac t aa t cah t asc t rah t asr t rad t ar t crp t rcd t rsh t ras t rp t chr t ras dqx v v ioh iol v v ih il addr v v ih il v v ih il ras# v v ih il t oe t od oe# t ord casl#/cash# -6 symbol min max units t oe 15 ns t off 3 15 ns t ord 0 ns t rac 60 ns t rad 15 ns t rah 10 ns t ras 60 10,000 ns t rcd 20 ns t rp 40 ns t rsh 15 ns
256k x 16 fpm dram micron technology, inc., reserves the right to change products or specifications without notice. w03.pm5 C rev.3/97 ? 1997, micron technology, inc. 256k x 16 fpm dram 18 technology, inc. 40-pin plastic soj (400 mil) da-6 .399 (10.13) .405 (10.29) 1.023 (25.98) .445 (11.30) .050 (1.27) typ pin #1 index .020 (0.51) .015 (0.38) .025 (0.64) min .380 (9.65) seating plane 1.029 (26.14) .950 (24.13) .360 (9.14) .435 (11.05) .090 (2.29) .105 (2.67) .150 (3.81) .138 (3.51) .037 (0.94) max dambar protrusion .026 (0.66) .032 (0.81) note: 1. all dimensions in inches (millimeters) max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900, micron datafax: 208-368-5800 e-mail: prodmktg@micron.com , internet: http://www.micron.com , customer comment line: 800-932-4992

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